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2nd IEEE Electronic Systems Test Workshop (ESTW 2005)
November 10-11
Austin Convention Center
Austin, Texas

Co-Located with ITC 2005

http://testlab.ics.uci.edu/estw

CALL FOR PAPERS

Overview -- Paper Submissions

Overview

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The objective of the Electronic Systems Test Workshop (ESTW) is to bring together researchers in all of the fields related to the test of entire systems. The heterogeneous nature of electronic system design calls for coordination between different research communities in order to address the system test problem. Currently research in each related field is performed by largely distinct research communities including digital IC test, mixed-signal test, embedded systems test, hardware/software co-simulation, and software test. As a result, there has been little effort towards the development of a coherent science of system test. This workshop is intended to be a forum for the broad collaboration required to establish a research foundation for the field of system test.

The topics of interest include, but are not limited to:

  • Diagnosis : Resolution vs. Repair Cost
  • System-level Fault Tolerance
  • Self-Repairing Systems
  • Embedded System Testing
  • System-Level Built-In Self-Test
  • Hardware/Software Co-simulation
  • Testing of Concurrent/Globally Asynchronous Systems
  • System Fault Characterization
  • System-Level Functional Test
  • Integration Testing
  • On-line System Test
  • Testing of Real-Time Systems

Paper Submissions

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ESTW submissions must be made electronically in PDF format through the ESTW web site. Reference the ESTW web page for instructions on electronic submissions:

http://testlab.ics.uci.edu/estw

Authors should submit one PDF file which should contain the complete paper including the title and abstract. This file should not be more than 4 pages.

The proceedings of this workshop will not be published. Proceedings will be distributed to workshop attendees.


AUTHOR'S SCHEDULE

Deadline for submissions: July 8, 2005
Notification of acceptance: August 5, 2005
Deadline for camera ready version: September 9, 2005

Please feel free to contact the program chair Ian G. Harris at harris@ics.uci.edu, if you have any questions.

General Chair: Tony Ambler
Department of Electrical Engineering and Computer Science
University of Texas, Austin
Ph: 521-471-6179, Fax: 521-471-6179
Email: ambler@mail.utexas.edu

Program Chair: Ian G. Harris
Department of Computer Science
University of California Irvine
Ph: 949-824-8842, Fax: 949-824-4056
Email: harris@ics.uci.edu

For more information, visit us on the web at: http://testlab.ics.uci.edu/estw

The 2nd IEEE Electronic Systems Test Workshop (ESTW 2005) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society– Test Technology Technical Council

TTTC CHAIR
André IVANOV
University of British Columbia– Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

SENIOR PAST CHAIR
Yervant ZORIAN
Virage Logic– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


TTTC 2ND VICE CHAIR
Michel RENOVELL
LIRMM– France
Tel. +33 467 418 523
E-mail renovell@lirmm.fr

FINANCE CHAIR
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

IEEE DESIGN & TEST EIC
Rajesh K. GUPTA
University of California, Irvine– USA
Tel. +1-949-824-8052
E-mail gupta@uci.edu

TECHNICAL MEETINGS
Cheng-Wen WU

National Tsing Hua Univ.– Taiwan
Tel. +886-3-573-1154
E-mail cww@computer.org

TECHNICAL ACTIVITIES
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica– Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

ASIA & SOUTH PACIFIC
Hideo FUJIWARA
Nara Inst. of Science and Technology– Japan
Tel. +81-74-372-5220
E-mail fujiwara@is.aist-nara.ac.jp

LATIN AMERICA
Marcelo LUBASZEWSKI
Federal Univ. of Rio Grande do Sul (UFRGS)– Brazil
Tel. +34-93-401-6603
E-mail luba@vortex.ufrgs.br

NORTH AMERICA
William R. MANN
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic, Inc.– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

 

PAST CHAIR
Paolo PRINETTO
Politecnico di Torino– Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 1ST VICE CHAIR
Adit D. SINGH
Auburn University– USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

SECRETARY
Christian LANDRAULT
LIRMM– France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Rob AITKEN
Artisan Components– USA
Tel. +1-408-548-3297
E-mail aitken@artisan.com

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic, Inc.– USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

Univ. of Piraeus– Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys– USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Joan FIGUERAS
Univ. Politècnica de Catalunya– Spain
Tel. +55-51-228-1633, Ext. 4830
E-mail figueras@eel.upc.es

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut– Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
Michael NICOLAIDIS
iRoC Technologies– Greece
Tel. +33-4-381-20763
E-mail michael.nicolaidis@iroctech.com

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino– Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it


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